View AS7C251MNTD18A-200TQI_6756145.PDF datasheet online --- IC-ON-LINE

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december 2002 advance information

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tm features ? organization: 1,048,576 words 18 bits ntd ?1 architecture for efficient bus operation fast clock speeds to 250 mhz in lvttl/lvcmos fast clock to data access: 2.6/2.8/3/3.4 ns fast oe access time: 2.6/2.8/3/3.4 ns fully synchronous operation flow-through or pipelined mode asynchronous output enable control 1. ntd tm is a trademark of alliance semiconductor corporation. available in 100-pin tqfp and 165-ball bga package byte write enables clock enable for operation hold multiple chip enable s for easy expansion 2.5v core power supply self-timed write cycles interleaved or linear burst modes snooze mode for standby operation logic block diagram selection guide -250 -225 -200 -166 units minimum cycle time 4 4.4 5 6 ns maximum pipelined clock frequency 250 225 200 166 mhz maximum pipelined clock access time 2.6 2.8 3.0 3.4 ns maximum operating current 425 400 370 340 ma maximum standby current 110 110 110 90 ma maximum cmos standby current (dc) 70 70 70 70 ma

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pin and ball assignment 165-ball bga - top view 100-pin tqfp - top view 1 2 3 4 5 6 7 8 9 10 11 a *) adv/ld b nc *)
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functional description the as7c251mntd18a family is a high performance cmos 16-mbit synchronous static random acce ss memory (sram) organized as 1,048,576 words 18 bits and incorporates a late late write. this variation of the 16mb+ synchronous sram uses the no turnaround delay (ntd ? ) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. in a norm al pipelined burst device, the wr ite data, command, and address are all applied to the device on the same clock edge. if a read command follow s this write command, the system must wait for two 'dead' cycles for valid data to become available. these dead cycles can significantly reduce overall bandwidth for applications requiring random access or r ead-modify- write operations. ntd ? devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow- through read latency. write data is applied two cycles after the write command and address, allowi ng the read pipeline to clear . with ntd ? , write and read operations can be used in any order without producing dead bus cycles. assert r/w low to perform write cycles. byte write enable controls write acce ss to specific bytes, or can be tied low for full 18 bit wri tes. write enable signals, along with the write address, are registered on a rising edge of the clock. writ e data is applied to the device two clock cycles later. unlike some asynchronous srams, output enable oe does not need to be toggled for write operations; it can be tied low for normal operations. outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. in pipe lined mode, a two cycle deselect latency allows pending re ad or write operations to be completed. use the adv (burst advance) input to perform burst read, write an d deselect operations. when adv is high, external addresses, c hip select, r/w pins are ignored, and internal address counters increm ent in the count sequence specified by the lbo control. any device operations, including burst, can be stalled using the cen =1, the clock enable input. the as7c251mntd18a operates with a 2.5v 5% power supply for the device core (v dd ). these devices are available in a 100-pin tqfp package and 165 bga ball grid array package. capacitance burst order parameter symbol signals test conditions max unit input capacitance c in address and control pins v in = 0v 5 pf i/o capacitance c i/o i/o pins v in = v out = 0v 7 pf interleaved burst order lbo = 1 linear burst order lbo = 0 a1a0 a1a0 a1a0 a1a0 a1a0 a1a0 a1a0 a1a0 starting address 0 0 0 1 1 0 1 1 starting address 0 0 0 1 1 0 1 1 first increment 0 1 0 0 1 1 1 0 first increment 0 1 1 0 1 1 0 0 second increment 1 0 1 1 0 0 0 1 second increment 1 0 1 1 0 0 0 1 third increment 1 1 1 0 0 1 0 0 third increment 1 1 0 0 0 1 1 0

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signal descriptions absolute maximum ratings stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, an d functional operation of the device at these or any other conditions outside those indica ted in the operational sections of this specification is not im plied. exposure to absolute maximum rating conditions may affect reliability. signal i/o properties description clk i clock clock. all inputs except oe , ft , lbo , and zz are synchronous to this clock. cen i sync clock enable. when de-asserted high, the clock input signal is masked. a, a0, a1 i sync address. sampled when all chip enables are active and adv/ld is asserted. dq[a,b] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 , ce1, ce2 isync synchronous chip enables. sampled at the rising edge of clk, when adv/ld is asserted. are ignored when adv/ld is high. adv/ld isync advance or load. when sampled high, the internal burst address counter will increment in the order defined by the lbo input value. (refer to table on page 2) when low, a new address is loaded. r/w isync a high during load initiates a read operation. a low during load initiates a write operation. is ignored when adv/ld is high. bw[a,b] isync byte write enables. used to control write on individual bytes. sampled along with write command and burst write. oe i async asynchronous output enable. i/o pins are not driven when oe is inactive. lbo istatic count mode. when driven high, count sequ ence follows intel xor convention. when driven low, count sequence follows linear conv ention. this input should be static when the device is in operation. ft istatic flow-through mode.when low, enables single register flow-through mode. connect to v dd if unused or for pipelined operation. tdo o sync serial data-out to the jtag circuit. delivers data on the negative edge of tck. (bga only) tdi i sync serial data-in to the jtag circuit. sampled on the rising edge of tck. (bga only) tms i sync this pin controls the test access port state machine. sampled on the rising edge of tck. (bga only) tck o sync serial data-out to the jtag circuit. delivers data on the negative edge of tck. (bga only) zz i async snooze. places device in low power mode ; data is retained. connect to gnd if unused. nc - - no connects. parameter symbol min max unit power supply voltage relative to gnd v dd , v ddq ?0.3 +3.6 v input voltage relative to gnd (input pins) v in ?0.3 v dd + 0.3 v input voltage relative to gnd (i/o pins) v in ?0.3 v ddq + 0.3 v power dissipation p d ?1.8w dc output current i out ?50ma storage temperature (plastic) t stg ?65 +150 o c temperature under bias (junction) t bias ?65 +150 o c

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synchronous truth table key: x = don?t care, l = low, h = high state diagram for ntd sram recommended operating conditions ce0 ce1 ce2 adv/ld r/w bw[a,b] oe cen address source clk operation h x x l x x x l na l to h deselect, high-z x l x l x x x l na l to h deselect, high-z x x h l x x x l na l to h deselect, high-z l h l l h x x l external l to h begin read lhl l l l xlexternal l to hbegin write xxx h x x 1 1 should be low for burst write unless specific bytes need to be inhibited x l burst counter l to h burst 2 2 refer to state diagram below. x x x x x x x h stall l to h inhibit the clk parameter symbol min nominal max unit supply voltage v dd , v ddq 2.35 2.5 2.65 v gnd 0.0 0.0 0.0 input voltages address and control pins v ih 2.0 ? v dd + 0.3 v v il ?0.5 1 1 v il min = ?2.0v for pulse width less than 0.2 x t rc . ?0.4 i/o pins v ih 2.0 ? v ddq + 0.3 v v il -0.5 1 ?0.4 ambient operating temperature t a 0?70 c & & * * ) & ) * & & ) & * ) ) ) * * * ) &

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dc electrical characterist ics for 2.5v i/o operation parameter sym test conditions 250 225 200 166 unit min max min max min max min max input leakage current 1 1 i cc given with no output loading. i cc increases with faster cycle times and greater output loading. | i li |v dd = max, v in = gnd to v dd ?2 ? 2 ?2 ? 2a output leakage current | i lo | oe v ih, v dd = max, v out = gnd to v dd -1 1 -1 1 -1 1 -1 1 a operating power supply current i cc ce = v il , ce = v ih , ce = v il , f = f max, i out = 0 ma ? 425 ? 400 ? 370 ? 340 ma standby power supply current 2 2 lbo pin has an internal pull-up, and input leakage = 10 ma. i sb deselected, f = f max ? 110 ? 110 ? 110 ? 90 ma i sb1 deselected, f = 0 , all v in 0.2v or (v dd , v ddq ) - 0.2v ?70? 70?70? 70 i sb2 deselected, f = f max , zz (v dd , v ddq ) - 0.2v, all v in v il or v ih ?30? 30?30? 30 output voltage v ol i ol = 2 ma, v ddq = 2.65v ? 0.7 ? 0.7 ? 0.7 ? 0.7 v v oh i oh = ?2 ma, v ddq = 2.35v 1.7 ? 1.7 ? 1.7 ? 1.7 ? v

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timing characteristics over operating range parameter sym 250 225 200 166 unit notes 1 1 see ?notes? on page 17 min max min max min max min max clock frequency f max - 250 225 - 200 - 166 mhz cycle time (pipelined mode) t cyc 4-4.4-5-6- ns cycle time (flow-through mode) t cycf 6.5 - 6.9 - 7.5 - 8.5 - ns clock access time (pipelined mode) t cd -2.6 - 2.8-3.0-3.4 ns clock access time (flow-through mode) t cdf -6.5 - 6.9-7.5-8.5 ns output enable low to data valid t oe -2.6 - 2.8-3.0-3.4 ns clock high to output low z t lzc 0 - 0 - 0 - 0 - ns 2, 3, 4 data output invalid from clock high t oh 1.5 - 1.5 - 1.5 - 1.5 - ns 4 output enable low to output low z t lzoe 0 - 0 - 0 - 0 - ns 2, 3, 4 output enable high to output high z t hzoe -2.6 - 2.8-3.0-3.4 ns2, 3, 4 clock high to output high z t hzc -2.6 - 2.8-3.0-3.4 ns2, 3, 4 clock high to output high z t hzcn -1.5 - 1.5-1.5-1.5 ns5 clock high pulse width t ch 1.5 - 1.8 - 1.8 - 1.8 - ns 8 clock low pulse width t cl 1.5 - 1.8 - 1.8 - 2.2 - ns 8 address and control setup to clock high t as 1.2 - 1.4 - 1.4 - 1.5 - ns 9 data setup to clock high t ds 1.2 - 1.4 - 1.4 - 1.5 - ns 9 write setup to clock high t ws 1.2 - 1.4 - 1.4 - 1.5 - ns 9 chip select setup to clock high t css 1.2 - 1.4 - 1.4 - 1.5 - ns 9 address hold from clock high t ah 0.3 - 0.4 - 0.4 - 0.5 - ns 9 data hold from clock high t dh 0.3 - 0.4 - 0.4 - 0.5 - ns 9 write hold from clock high t wh 0.3 - 0.4 - 0.4 - 0.5 - ns 9 chip select hold from clock high t csh 0.3 - 0.4 - 0.4 - 0.5 - ns 9 clock enable setup to clock high t cens 1.2 - 1.4 - 1.4 - 1.5 - ns 9 clock enable hold from clock high t cenh 0.3 - 0.4 - 0.4 - 0.5 - ns 9 adv setup to clock high t advs 1.2 - 1.4 - 1.4 - 1.5 - ns 9 adv hold from clock high t advh 0.3 - 0.4 - 0.4 - 0.5 - ns 9

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ieee 1149.1 serial boundary scan (jtag) the sram incorporates a serial boundary scan test access port (tap). the port operates in accord ance with ieee standard 1149.1- 1990 but does not have the set of functions requir ed for full 1149.1 compliance. the inclusion of these functions would place an added d elay in the critical speed path of the sram. the tap co ntroller functionality does not conflict wi th the operation of other devices using 1 149.1 fully compliant taps. it uses jedec-standard 2.5v i/o logic levels. the sram contains a tap controller, instruction register, bo undary scan register, bypass register, and id register. disabling the jtag feature if the jtag function is not being implemented, its pins/balls can be left unconnected. at power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used with only the tap co ntroller. all inputs are captured on the ri sing edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tap controller receives commands from tms input. it is sampled on the rising edge of tck. you can leave this pin/ball uncon nected if the tap is not used. the pin/ball is pulled up internally, resulting in a logic high level. 80,91& 0,8&91& %:1+,91& ;1,91& 08%91& ;1,91& % , 1&9% 80,9& 0,8&9& %:1+,9& ;1,9& 08%9& ;1,9& &89,%,( 1 ,%,9 <1 % , &9% ,=$ != => ?,#% =?,
. tap controller state diagram t ap controller block diagram % ! ! ' % ! ! ' 2 2 . . . *'%!& 1 ?! & *'& 1 ! & $ .. . .. ,1 ,#% ,
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test data-in (tdi) the tdi pin/ball serially inputs information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instr uction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the ta p is unused in an application . tdi is connected to the most significant bit (msb) of an y register. (see the tap controller block diagram.) test data-out (tdo) the tdo output pin/ball serially clocks data-out from the regist ers. the output is active depending upon the current state of t he tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (s ee the tap controller state diagram.) performing a tap reset you can perform a reset by forcing tms high (v dd ) for five rising edges of tck. this reset do es not affect the operation of the sram and can be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and td o pins/balls. they allow data to be scanne d into and out of the sram test circuit ry. only one register can be selected at a time through the instruction regist er. data is serially loaded into the tdi pin/ball on the risin g edge of tck. data is output on the tdo pin/ball on the falling edge of tck. instruction register you can serially load three-bit instructions into the instruction register. the register is loaded when it is placed between th e tdi and tdo pins/ balls as shown in the tap controller block diagram. the instructio n register is loaded with the id code instruction at power up and also if the controller is placed in a reset state, as described in the previous section. when the tap controller is in the capture-ir state, the two leas t significant bits are loaded with a binary ?01? pattern to all ow for fault isolation of the board-level series test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass regi ster is a single-bit register that can be placed between the tdi and tdo pins/balls. this allows data to be shifte d through the sram with minimal de lay. the bypass register is set low (vss) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bi directional pins/balls on the sr am. the x36 configuration has a 70-bit-long register and the x18 configurat ion has a 51-bit-long register. the boundary scan register is loaded with the contents of the ram i/o ring when the ta p controller is in the capture-dr state a nd is then placed between the tdi and tdo pins/balls when the controller is moved to the shift-dr state. the extest, sample/reload, and sa mple z instructions can be used to cap ture the contents of the i/o ring. the boundary scan order table shows the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the most significant bit (msb) of the register is connected to tdi, and the least significant bit (lsb) is connected t o tdo. identification (id) register the id register has a vendor code and other information describe d in the identification register definitions table. the id regi ster is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the i dcode is hardwired into the sram and can be shifted out wh en the tap controller is in the shift-dr state.

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tap instruction set eight different instructions are possible with the 3-bit instruction register. all comb inations are listed in the instruction c odes table. three of these instructions are reserved and should not be used. note that the tap controller used in this sr am is not fully compliant to the 1149.1 conv ention because some of the mandatory 11 49.1 instructions are not fully implemented. the tap controller cannot be used to load address, data , or control signals into the sr am and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/ preload. instead, it performs a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap control ler during the shift-ir state when the instruction register is placed between tdi a nd tdo. during this state, instructions are shifted through the instruction regi ster through the tdi and tdo pins/balls. to execute the instru ction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest the extest instruction, which executes whenever the instruction re gister is loaded with all 0s, is not implemented in this sram tap controller. the tap controller, however, does recognize an all-0 instruction. when an ex test instruction is loaded into the ins truction register, the sram responds as if a sample/preload instruction has been loaded. unlike the sa mple/preload instructio n, extest places the sram outputs in a high-z state. extest is a mandatory 1149.1 in struction. this device, therefore , is not compliant with 1149.1. idcode the idcode instruction is loaded into the instruction register u pon power-up or whenever the ta p controller is given a test log ic reset state. the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the ins truction register between the tdi and tdo pins/balls and allows the idcode to be shifted out of the device when the tap controller enters the shi ft-dr state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and td o pins/balls when the tap cont roller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload when the sample/preload instruction is loaded into the instruction register and the ta p controller is in the capture-dr state, a snapshot of data on the inputs and bidirect ional pins/balls is captured in the boundary scan register. note that the sample/preload is a 11 49.1 mandatory instruction, but the preload portion of this instructio n is not implemented in this device. the tap controller, there fore, is not fully 1149.1 compliant. be aware that the tap controller clock can operate only at a freque ncy up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the cloc k frequencies, it is possible that during the capture-dr state , an input or output can undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm t he device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long en ough to meet the tap controller?s capture se tup plus hold time (t cs plus t ch ). the sram clock input might not be cap tured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instru ction. if this is an issue, it is possible to capture all othe r signals and ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap i nto the shift-dr state. this places the bou ndary scan register between the tdi and tdo pins. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a s ample/ preload instruction will have the same effect as the pause-dr command. bypass the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. when the bypass instruction is loaded in the instruction register and the tap is placed in a shift-dr state, the bypass registe r is placed between tdi and tdo.

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reserved do not use a reserved instruction.these instructions are not implemented but are reserved for future use. tap timing diagram tap ac electrical characteristics for notes 1 and 2, +10 o c < t j < +110 o c and +2.4v < v dd < +2.6v. description symbol min max units clock clock cycle time t thth 100 ns clock frequency f tf 10 mhz clock high time t thtl 40 ns clock low time t tlth 40 ns output times tck low to tdo unknown t tlox 0ns tck low to tdo valid t tlov 20 ns tdi valid to tck high t dvth 10 ns tck high to tdi invalid t thdx 10 ns setup times tms setup t mvth 10 ns capture setup t cs 1 1 t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 2 test conditions are specified using the load in the figure tap ac output load equivalent. 10 ns hold times tms hold t thmx 10 ns capture hold t ch 1 10 ns 2345 ,:, , ,: ,:,: #-,: ,:#; -,: ,:; , ; , - , !a b,
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tap dc electrical characterist ics and operating conditions (+10 o c < t j < +110 o c and +2.4v < v dd < +2.6v unless otherwise noted) 1. all voltage referenced to v ss (gnd). 2. overshoot: v ih (ac) v dd + 1.5v for t t khkh /2 undershoot: v il (ac) -0.5 for t t khkh /2 power-up: v ih +2.6v and v dd 2.4v and v ddq 1.4v for t 200ms during normal operation, v ddq must not exceed v dd . control input signals (such as ld , r/w , etc.) may not have pulsed widths less than t khkl (min) or oper- ate at frequencies exceeding f kf (max). description conditions symbol min max units notes input high (logic 1) voltage v ih 1.7 v dd + 0.3 v 1, 2 input low (logic 0) voltage v il -0.3 0.7 v 1, 2 input leakage current 0v v in v dd il i -5.0 5.0 a output leakage current outputs disabled, 0v v in v ddq (dqx) il o -5.0 5.0 a output low voltage i olc = 100 av ol1 0.2 v 1 output low voltage i olt = 2ma v ol2 0.7 v 1 output high voltage i ohs = -100 av oh1 2.1 v 1 output high voltage i oht = -2ma v oh2 1.7 v 1 input pulse levels. . . . . . . . . . . . . . . vss to 2.5v input rise and fall times. . . . . . . . . . . . . . . 1 ns input timing reference levels. . . . . . . . . . 1.25v output reference levels . . . . . . . . . . . . . . 1.25v test load termination supply voltage. . . . 1.25v tap ac test conditions tap ac output load equivalent , 4 ? / @4 ? .4- +

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identification register definitions scan register sizes instruction codes instruction field 1m x 18 description revision number (31:28) xxxx reserved for version number. device depth (27:23) xxxxx defines the depth of 1mb words. device width (22:18) xxxxx defines the width of x18 bits. device id (17:12) xxxxxx reserved for future use. jedec id code (11:1) 00000110100 allows unique identification of sram vendor. id register presence indicator (0) 1 indicates the presence of an id register. register name bit size instruction 3 bypass 1 id 32 boundary scan x18:51 x36:70 instruction code description extest 000 captures i/o ring contents. places the bo undary scan register between tdi and tdo. forces all sram outputs to high-z state. this instruction is not 1149.1-compliant. idcode 001 loads the id register with the vendor id c ode and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the bo undary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use. this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the bo undary scan register between tdi and tdo. does not affect sram operation. this in struction does not implement 1149.1 preload function and is therefore not 1149.1-compliant. reserved 101 do not use. this instruction is reserved for future use. reserved 110 do not use. this instruction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations.

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165-ball bga boundar y scan order (x18) bit #s signal name ball id 1sa 8p 2sa 9r 3sa 9p 4sa 10r 5sa 10p 6sa 11r 7sa 8r 8 dqa 10m 9dqa 10l 10 dqa 10k 11 dqa 10j 12 zz 11h 13 dqa 11g 14 dqa 11f 15 dqa 11e 16 dqa 11d 17 dqpa 11c 18 sa 11a 19 sa 10b 20 sa 10a 21 sa 9a 22 sa 9b 23 adv/ld 8a 24 oe 8b 25 cen 7a 26 r/w 7b 27 clk 6b bit #s signal name ball id 28 ce2 6a 29 bwa 5b 30 bwb 4a 31 ce1 3b 32 ce0 3a 33 sa 2a 34 sa 2b 35 dqb 2d 36 dqb 2e 37 dqb 2f 38 dqb 2g 39 ft 1h 40 dqb 1j 41 dqb 1k 42 dqb 1l 43 dqb 1m 44 dqpb 1n 45 lb0 1r 46 sa 3p 47 sa 3r 48 sa 4p 49 sa 4r 50 sa1 6p 51 sa0 6r 52 ? 53 ?

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key to switch ing waveforms timing waveform of read/write cycle e@;&f= * @==(! ge@f= * @ f.*) d !.

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nop, stall and deselect cycles e@;&f= * @==(! ge@f= * @ f. f.
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ac test conditions notes: 1) for test conditions, see ?ac test conditions?, figures a, b, c 2) this parameter measured with ou tput load condition in figure c. 3) this parameter is sampled, but not 100% tested. 4) t hzoe is less than t lzoe and t hzc is less than t lzc at any given temperature and voltage. 5) t ch measured high above v ih and t cl measured as low below v il 6) this is a synchronous device. all addresses must meet the sp ecified setup and hold times for all rising edges of clk. all ot her synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clk when chip is enabled. 7) write refers to r/w and bw[a,b] . 8) chip select refers to ce0 , ce1, and ce2 . ? 50 ?

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package dimensions 100-pin quad flat pack (tqfp) 165-ball bga (ball grid array) tqfp min max a1 0.05 0.15 a2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 d 13.90 14.10 e 19.90 20.10 e 0.65 nominal hd 15.90 16.10 he 21.90 22.10 l 0.45 0.75 l1 1.00 nominal 0 7 dimensions in millimeters ! ( .34i.4b54;c j." j.4 5 6 " 2 3 4 5 4 3 2 " 6 : + < * # 0 & k
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? copyright alliance semiconductor corporati on. all rights reserved. our three-point l ogo, our name and intelliwatt are tradema rks or registered trademarks of alliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to this document and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the data contained herein represents alliance?s best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without notice. if the product described herein is under development, significant changes to these specifications ar e possible. the information in this product data sheet is inte nded to be general descriptive in formation for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibility or liab ility arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including li ability or warranties related to fitness for a particular purpose, merchantability, or infringeme nt of any intellectual property rights, except as express agreed to in alliance?s terms and conditions of sale (which are available fr om alliance). all sa les of alliance product s are made exclusively according to alliance?s terms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights, ma sk works rights, trademarks, or any oth er intellectual property rights of alliance or th ird parties. allia nce does not authorize its products for use as critical components in life-supporting systems where a ma lfunction or failure may reasonably be expected to result i n significant injury to the user, and the inclusion of alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and ag rees to indemnify alliance against all claims arising from suc h use.

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ordering information part numbering guide 1. alliance semiconductor sram prefix 2. operating voltage: 25 = 2.5v 3. organization: 1m 4. ntd? = no turn-around delay. pipelined/flow-through mode (each device works in both modes) 5. organization: 18 = x 18 6. production version: a = first production version 7. clock speed (mhz) 8. package type: tq = tqfp; b = bga 9. operating temperature: c = commercial ( 0 c to 70 c); i = industrial ( -40 c to 85 c) package & width ?250 mhz ?225 mhz ?200 mhz ?166 mhz tqfp x18 as7c251mntd18a- 250tqc as7c251mntd18a- 225tqc as7c251mntd18a- 200tqc as7c251mntd18a- 166tqc as7c251mntd18aa- 225tqi as7c251mntd18a- 200tqi as7c251mntd18a- 166tqi bga x18 as7c251mntd18a- 250bc as7c251mntd18a- 225bc as7c251mntd18a- 200bc as7c251mntd18a- 166bc as7c251mntd18a- 225bi as7c251mntd18a- 200bi as7c251mntd18a- 166bi as7c 25 1m ntd 18 a ?xxx tq or b c/i 1 23 45678 9

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